This invention relates to regulating the work of multiple processors within parallel regions of a machine instruction sequence.
A parallel region is one which contains independent blocks that can be executed concurrently by different processors to produce the same result as when all blocks are executed by a single processor. A given machine instruction sequence may include any arbitrary arrangement of parallel regions.
Some types of instruction sequences can be executed by a technique in which identical copies of the sequence are loaded into all of the processors. A central controller steps the processors through the sequence; for each instruction in the sequence, the controller causes each processor either to execute the instruction or to bypass execution of the instruction.
In another approach, applicable for example to the iterations of a do loop, a central controller assigns different iterations to different processors.
In a more broadly applicable scheme, the segments of code are stored in memory; a central scheduler picks up each segment of code in turn and delivers it to a processor for execution.